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New SoC Technology with Circuitry of 65nm Announced
Posted: 03-Dec-2002 [Source: Toshiba press release]

[Toshiba and Sony announce new chip-making technology offering smaller size and higher levels of performance for use in mobile devices.]

Tokyo -- Toshiba Corporation and Sony Corporation today announced the world's first 65-nanometer (nm) CMOS process technology for embedded DRAM system LSIs -- a major breakthrough in process technology for highly advanced, compact, single-chip system LSIs that will be only one-fourth the size of current devices while offering higher levels of performance and functionality.

The move to ubiquitous computing -- total connectivity at all times -- relies on high-performance equipment. These in turn require advanced SoC (system on chip) LSIs integrating ultra-high performance transistors and embedded high-density DRAM. In such devices, size and performance levels are directly related to process technology: finer lithography results in smaller devices that offer higher levels of performance. The new process technology announced by Toshiba and Sony and integration to a new level that allows bandwidths to be scaled up and the maximization of system performance.

Current system LSI devices on the market are produced with 130 nanometer process technologies. Toshiba, the recognized industry leader in advanced process technology, is the only company with mass production technology for 90nm process embedded DRAM system LSI, a technology it is currently deploying and that will meet ever increasing demand for more and more compact devices.

The new SoC technologies for 65nm process generation include: 1) a high-performance transistor with the world's fastest switching speed; 2) the world's smallest cell for embedded DRAM; and 3) the world's smallest cell for embedded SRAM.

The new process technology is the result of joint development of Toshiba Corporation and Sony Corporation of 90nm and 65nm CMOS process technology that was initiated in May 2001. Full details will be presented at the December 9 - 11 International Electron Devices Meeting (IEDM) in San Francisco.

Outline of new technology

1) High-performance transistor with 30nm gate length: Transistors in this technology have high nitrogen concentration plasma nitrided oxide-gate dielectrics to suppress gate leakage current. This optimization reduces leakage current approximately 50 times more efficiently than conventional SiO2 film and allows formation of an oxide with an effective thickness of only 1nm. Furthermore, Ni silicide is applied in the gate electrodes and source/drain regions to attain low resistance and to reduce junction leakage current. Shallow extension formation optimizing ultra-low energy ion implantation, spike RTA and offset spacer process successfully suppresses the short channel effect of MOSFET and achieves superior roll-off characteristics. An excellent switching speed of 0.72psec for NMOSFET and 1.41psec for PMOSFET at 0.85V (Ioff=100nA/um), were obtained. Currently available Hi-NA193-nm lithography with alternating phase shift mask and slimming process provides 30nm gate lengths. 2) Embedded DRAM cell: High-speed data processing requires a single-chip solution integrating a microprocessor and embedded large volume memory. Toshiba is the only semiconductor vendor able to offer commercial trench-capacitor DRAM technology for 90nm-generation DRAM-embedded System LSI. Toshiba and Sony have utilized 65nm process to technology to fabricate an embedded DRAM with a cell size of 0.11um2, the world's smallest, which will allow DRAM with a capacity of more than 256Mbit to be integrated on a single chip. 3) Embedded SRAM cell: SRAM is sometimes used as cache memory in SoC systems. The Hi-NA193-nm lithography with alternating phase shift mask and the slimming process combined with the non-slimming trim mask process will achieve the world's smallest embedded SRAM cell in the 65nm generation an areas of only 0.6um2. 4) 180nm Multi layer wiring: In order to reduce the chip size, it is important reduce the pitch of the first metal of the lowest layer. The new technology has a 180nm pitch, a 75% shrink from the 90nm generation. To reduce wiring propagation delay and power dissipation, a low-k dielectric material is adopted. The target effective dielectric constant of the interlayer dielectric is around 2.7.

Note: 1 nanometer = one billionth of a meter

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